Consider the thin integrated circuit (chip) of Problem 3.136. Instead of attaching the heat sink to the chip surface, an engineer suggests that sufficient cooling might be achieved by mounting the top of the chip onto a large copper (k = 400 W/m ? K) surface that is located nearby. The metallurgical joint between the chip and the substrate provides a contact resistance of Rt,c = 5 X 10-6 m2 ? K/W, and the maximum allowable chip temperature is 85°e. If the large substrate temperature is T2 = 25°C at locations far from the chip, what is the maximum allowable chip power dissipation qc?
This question was answered on: Jul 11, 2017
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